Substrate, manufacturing method of substrate, semiconductor element, and manufacturing method of semiconductor element

ABSTRACT

A semiconductor device is provided which is produced from a high-quality and large-area graphene substrate and is capable of fully exhibiting superior electronic properties that graphene inherently has. The semiconductor device is capable of realizing increased operation speed, reduced power consumption, and higher degree of integration, and thus is capable of improving the reliability and productivity. Electrical short circuit between a graphene layer ( 4 ) and a metal catalyst layer for growth of graphene is prevented by causing the metal catalyst layer to be absorbed as a compound/alloyed layer  5  at the interface between a substrate ( 1 ) and an oxide layer ( 2 ).

TECHNICAL FIELD

This invention relates to substrates and semiconductor elements. Inparticular, the invention relates to substrates comprising uniqueelectronic properties and optical characteristics, and excellentmechanical characteristics and chemical characteristics derived fromatomic layer thin films, and thus applicable to next-generationelectronics, optoelectronics, and spintronics, and also relates tosemiconductor elements using such substrates.

BACKGROUND ART

The recent information-oriented society is supported by semiconductorelements represented by silicon-based CMOSs (Complementary Metal-OxideSemiconductors). So far, the silicon semiconductor industry has achievedminiaturization by continuously reducing the limit of processability ofmicroprocessing technologies such as lithography, etching, anddeposition technologies from the order of micrometers to several tens ofnanometers, and has realized both high integration and high performance.However, the element size is bound to reach an atomic or molecular levelin near future, and physical limitation of semiconductor materials suchas silicon and existing element structures are pointed out. In order tobreak such deadlock, there exists a demand for novel element structuresbased on novel semiconductor materials or novel ideas. Particularly,atomic layer thin films of graphene or the like have recently beenattracting attention as a novel semiconductor material having a greatpotential to respond to this demand. The atomic layer thin films have apotential to realize novel elements capable of providing performancesexceeding those of existing elements by utilizing excellent physicalproperties thereof.

The term “atomic layer thin film” means an ultrathin film having athickness corresponding to several to a little more than 10 atoms, thatis, several nanometer to a little more than 10 nanometers. The atomiclayer thin film is ideally a monocrystal film. The most famous and basicone of the atomic layer thin films is graphene. Graphene is a monolayerof graphite which is a layered material consisting only of sp²hybridized carbon, and is stable planar monoatomic layer material.Although the term graphene usually means a monolayer of graphite, itoften includes those with two or more layers. Graphene consisting of asingle layer is referred to as monolayer graphene, the one consisting oftwo layers is referred to as bilayer graphene, and the one consisting ofthree layers is referred to as trilayer graphene, and those consistingof up to about 10 layers are collectively referred to as few-layergraphene. At the same time, those other than the monolayer grapheneshall be represented as multilayer graphene. The graphene has astructure of a honeycomb-like pseudo two-dimensional sheet in whichregular hexagonal six-carbon rings with a carbon atom at each apex arearranged tightly. The carbon-to-carbon distance is about 1.42 angstroms(0.142 nm), the layer thickness is 3.3 to 3.4 angstroms (0.33 to 0.34nm) when the base is graphite, and about 10 angstroms (1 nm) when thebase is other substrates. The size of the graphene plane can be various.For example, the length of one piece of graphene may assume varioussizes from a molecular size of a nanometer order to theoretically aninfinite size. Further, the graphene has three axes of symmetry in theplane due its honeycomb structure. Therefore, when the structure isrotated by 120 degrees about a certain point, it will be overlapped withthe original structure.

The electronic state of graphene can be described by a Dirac equation ina low energy region. In this respect, graphene presents a markedcontrast to other materials than graphene the electronic state of whichcan be described well by a Schrodinger equation. The electronic energyof graphene has a linear dispersion relation to wave number in thevicinity of the K-point. More specifically, the electronic energy ofgraphene can be represented by two straight lines having positive andnegative slopes corresponding to a conduction band and a valence band.The point where these straight lines intersect is called Dirac point,where electrons of graphene have peculiar electronic properties,behaving as fermions with an effective mass of zero. For this reason,grapheme exhibits a theoretical mobility of 10⁶ cm²V⁻¹s⁻¹ and an actualmobility of 2×10⁵ cm²V⁻¹s⁻¹, both of which are the maximum values in theexisting materials. Moreover, graphene is characterized by having lowtemperature dependency. Graphene is basically a metal or semimetal witha band gap of zero. However, when the size becomes an order ofnanometers, the band gap will become wide, and the graphene becomes asemiconductor having a finite band gap, depending on the width and edgestructure of the graphene. A bilayer graphene has a band gap of zerowhen there is no perturbation. However, when such perturbation as tobreak the mirror symmetry between the two graphene layers, for examplean electric field is applied, the graphene will have a finite band gapaccording to the magnitude of the electric field.

The most basic element utilizing the aforementioned features is afield-effect transistor (FET) using graphene for a channel. The firstreport on a graphene FET is found in K. S. Novoselov, A. K. Geim, S. V.Morozov, D. Jiang, Y. Zhang, S. V. Dubonos, I. V. Grigorieva, and A. A.Firsov, “Electric Field Effect in Atomically Thin Carbon Films”,Science, 306, 22 October 2004, p 666-669 (Non-Patent Document 1). TheFET described in this Non-Patent Document 1 has a structure in which agraphene piece used for a channel is arranged on a highly doped siliconsubstrate with silicon oxide interposed therebetween, and two goldelectrodes are connected to the opposite ends of the graphene piece toprovide source and drain electrodes, while the highly doped silicon isused as a back gate electrode. The graphene piece is obtained by using astandard lithography and etching technique to cut out a graphene piecefrom the surface of highly oriented pyrolytic graphite (HOPG) and a thinpiece is peeled off with the use of an adhesive tape to obtain a finalgraphene piece. The graphene channel of this element has a large widthof at least 80 nanometers, no quantum size effect caused by the edgestructure does not occur in this metal in the same state as themacro-scale bulk state. The reason why the field effect occurs not inthe semiconductor but in the metallic graphene is that the used metallicgraphene, consisting of one to several layers, is very thin in thethickness direction, and hence the electric field applied via the gateelectrode is able to overwhelm the shielding by carrier in the graphenechannel. Since the graphene channel is intentionally not doped, the samenumber of conduction electrons and electron holes exist as the carrierwhen the gate voltage is zero and no electric field exists. When thegate voltage is applied in a negative direction, the electrons aredepleted and the electron holes are accumulated to perform conduction.Whereas, when the gate voltage is applied in a positive direction, theelectron holes are depleted and the electrons are accumulated to performconduction. This means that while the element exhibits so-calledambipolar conduction, the element is not completely turned off since theelectron holes and the electrons cannot be depleted simultaneously.Accordingly, this graphene element does not have high performance fromthe viewpoint of performance index of typical field-effect transistors.Nevertheless, metallic graphene has attracted attention as aninteresting system in the field of pure physics since metallic graphenebehaves as ideal and peculiar two-dimensional gas.

At present, graphene elements are mostly manufactured using the existingmicroprocessing technologies. For example, as described in Non-PatentDocument 1, peeled graphene is obtained by a so-called mechanicalexfoliation method in which natural graphite or HOPG (Highly OrientedPyrolytic Graphite) is thinly peeled off with the use of an adhesivetape and the peeled piece is attached onto an appropriate substrate.This method is satisfactory for producing several to several tens ofseparate elements, for example for the purpose of verifying possibleperformance of the elements in the laboratory stage. However, the methodis not suitable for mass production and hence is virtually impossible tobe used industrially. A potential method for mass producing grapheneelements is a method in which a microprocessing technology is applied toa substrate carrying a large-area graphene on its surface that is usedas a starting material. The method using the graphene substrate as thestarting material has an advantage that a microprocessing technologycultivated in the semiconductor industry using silicon substrates can beapplied to some extent while there exists limitation in the currentstate. There are principally two different methods for fabricating agraphene on a substrate. One of them is a method of forming a graphenethin film on a substrate of silicon carbide (SiC), and the other one isa CVD (Chemical Vapor Deposition) method using a metal catalyst.According to the former method as disclosed in Konstantin V. Emtsev,Aaron Bostwick, Karsten Horn, Johannes Jobst, Gary L. Kellogg, LotharLey, Jessica L. McChesney, Taisuke Ohta, Sergey A. Reshanov, JonasRohrl, Eli Rotenberg, Andreas K. Schmid, Daniel Waldmann, Heiko B. Weber& Thomas Seyller, “Towards wafer-size graphene layers by atmosphericpressure graphitization of silicon carbide”, nature materials, volume 8,March 2009, p 203-207 (Non-Patent Document 2), monocrystal SiC is heatedto 1200° C. or higher so that the carbon in the surface of the SiC isonce released and then is restructured to epitaxially grow graphene,while the remaining surface silicon combines with oxygen in the heatedatmosphere to become volatile SiO or the like and is discharged.Accordingly, only the most superficial part of the SiC substrate is usedfor formation of graphene, while the other part remains as SiC. The SiC,having a large band gap, serves as an insulator substrate, and, as aresult, a graphene substrate comprising graphene formed on the surfaceof the SiC substrate as the insulator is obtained by thermal treatmentof the SiC substrate. A method of manufacturing graphene by the CVDprocess is described in Japanese Laid-Open Patent Publication No.2008-50228 (Patent Document 1), Japanese Laid-Open Patent PublicationNo. 2009-91174 (Patent Document 2), and Japanese Laid-Open PatentPublication No. 2009-107921 (Patent Document 3). The principle of theCVD process is that a hydrocarbon such as methane is thermallydecomposed on a metal-monocrystals or metal-film deposited substrate,and then the released carbon is restructured on the metal. In this case,the metal serves as a catalyst, and a transition metal is principallyused for this purpose. Although other atomic layer thin films thangraphene are also expected to have excellent electronic properties, veryfew such films are known and, moreover, knowledge about the structureand physical properties thereof is extremely limited. An ALD (AtomicLayer Deposition) process is known as a method of producing an atomiclayer thin film. However, this method is applicable to only limitedsemiconductors and metals, and requires a large-scale system and highcost.

DISCLOSURE OF THE INVENTION

However, the graphene manufacturing methods as disclosed in PatentDocuments 1 to 3 and other currently available techniques have problemsas described below.

A first problem is that the substrate used for CVD growth of graphenecannot be used directly for production of elements. This is attributableto the fact that the graphene is entirely in contact with a metal. Evenif an element is produced from this material, electric current will flowpreferentially through the metal and very little current will flowthrough the graphene. This is because a metal catalyst is indispensablefor CVD growth of large-area graphene, and the graphene grows along themetal surface, whereby the graphene layer is attached so firmly to themetal surface that they cannot be separated from each other.

A second problem resides in that conventional CVD grown graphene hasmuch higher sheet resistance than an ideal graphene, and has very poormobility. This is attributable to the fact that many lattice defects areintroduced in the graphene, structural breaks or wrinkles are generated,or a contaminant inhibiting electron transport adheres to the graphene.This is because, according to a conventional technique, the graphenemust be once peeled off from a substrate for growth by dissolving acatalyst metal with an etchant such as an acid or iron oxide solutionand then transferred to another substrate in order to produce anelement. The graphene inevitably suffers from structural break orcontamination with charge or magnetic contaminants during this transfer.

A third problem resides in that fabrication of low-cost and versatileatomic layer thin films is not known in the currently availableconventional technologies. The aforementioned ALD process requires hugecost for introduction and maintenance of a manufacturing system, and yetapplicable semiconductors and metals are limited. Further, it is verydifficult to obtain an ultrathin atomic layer with a thicknesscorresponding to several atoms, even if the ALD process can be applied.

This invention has been made in order to solve these problems, and afirst object of the invention is to provide a high-quality, large-areagraphene substrate which is directly usable for production ofsemiconductor devices, and a semiconductor device produced using such agraphene substrate. A second object of the invention is to provide anatomic layer thin film substrate which is produced from the graphenesubstrate and is directly usable for production of semiconductordevices, and a semiconductor device produced using such an atomic layerthin film substrate.

Means for Solving the Problems

In order to solve the aforementioned problems, a first aspect of thisinvention provides a substrate formed by stacking, on a semiconductor ormetal layer, a graphene layer formed by chemical vapor deposition usinga metal catalyst, an oxide layer for diffusing the metal catalyst, and acompound or alloyed layer formed by combination or alloying between themetal catalyst and the semiconductor or metal layer.

A second aspect of this invention provides a substrate formed bystacking, on a semiconductor or metal layer, an atomic layer thin filmformed by reducing an oxide layer with a graphene layer formed bychemical vapor deposition using a metal catalyst, the oxide layer fordiffusing the metal catalyst, and a compound or alloyed layer formed bycombination or alloying between the metal catalyst and the semiconductoror metal layer.

A third aspect of this invention provides a substrate formed bystacking, on a semiconductor or metal layer, a graphene layer formed bychemical vapor deposition using a metal catalyst, an atomic layer thinfilm formed by reducing an oxide layer with the graphene layer, theoxide layer for diffusing the metal catalyst, and a compound or alloyedlayer formed by combination or alloying between the metal catalyst andthe semiconductor or metal layer.

A fourth aspect of this invention is a semiconductor elementmanufactured with the substrate described above.

A fifth aspect this invention provides a manufacturing method of asubstrate including: (a) forming an oxide layer on a semiconductor ormetal layer; (b) forming a metal catalyst layer required forgraphitization on the oxide layer; (c) forming a graphene layer on themetal catalyst layer through thermal decomposition of a carbon sourceand cooling; and (d) performing heating to cause the metal catalystlayer to diffuse into the oxide layer and to cause the metal catalystlayer to be absorbed as a compound or alloyed layer by combination oralloying with the semiconductor or metal so that the graphene layerdirectly faces the oxide layer.

A sixth aspect of this invention provides a manufacturing method of asubstrate including: (a) forming an oxide layer on a semiconductor ormetal layer; (b) forming a metal catalyst layer required forgraphitization on the oxide layer; (c) forming a graphene layer on themetal catalyst layer through thermal decomposition of a carbon sourceand cooling; (d) performing heating to cause the metal catalyst layer todiffuse into the oxide layer and to cause the metal catalyst layer to beabsorbed as a compound or alloyed layer by combination or alloying withthe semiconductor or metal so that the graphene layer directly faces theoxide layer; and (e) performing further heating to form an atomic layerthin film on the oxide layer by reducing an upper layer of the oxidewith the graphene layer.

A seventh aspect of this invention provides a manufacturing method of asubstrate including: (a) forming an oxide layer on a semiconductor ormetal layer; (b) forming a metal catalyst layer required forgraphitization on the oxide layer; (c) forming a graphene layer on themetal catalyst layer through thermal decomposition of a carbon sourceand cooling; (d) performing heating to cause the metal catalyst layer todiffuse into the oxide layer and to cause the metal catalyst layer to beabsorbed as a compound or alloyed layer by combination or alloying withthe semiconductor or metal so that the graphene layer directly faces theoxide layer; and (f) performing further heating to form a compositeatomic layer thin film comprising a stacked structure including of anupper layer of the graphene layer and an atomic layer thin film byreducing an upper layer of the oxide layer with a lower layer of thegraphene layer.

An eighth aspect of this invention provides a manufacturing method of asemiconductor element including the manufacturing method of a substrateaccording to any one of the fifth to seventh aspects of the invention.

Advantageous Effects of the Invention

This invention is able to provide a high-quality, large-area graphenesubstrate which is directly usable for production of semiconductordevices, and a semiconductor device produced using such a graphenesubstrate.

This invention is also able to provide an atomic layer thin filmsubstrate which is produced from the graphene substrate and is directlyusable for production of semiconductor devices, and a semiconductordevice produced using such an atomic layer thin film substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a perspective view showing a graphene substrate 4A;

FIG. 1B is a perspective view showing an atomic layer thin filmsubstrate 6B;

FIG. 1C is a perspective view showing a composite atomic layer thin filmsubstrate 9C;

FIG. 2A is a perspective view showing a semiconductor element(field-effect transistor 14A) including a graphene layer;

FIG. 2B is a perspective view showing a semiconductor element(field-effect transistor 16B) including an atomic layer thin film;

FIG. 2C is a perspective view showing a semiconductor element(field-effect transistor 19C) including a composite atomic layer thinfilm;

FIG. 3A is a diagram showing a substrate manufacturing method accordingto this invention;

FIG. 3B is a diagram showing the substrate manufacturing methodaccording to this invention;

FIG. 3C is a diagram showing the substrate manufacturing methodaccording to this invention;

FIG. 3D is a diagram showing the substrate manufacturing methodaccording to this invention;

FIG. 3E is a diagram showing the substrate manufacturing methodaccording to this invention;

FIG. 3F is a diagram showing the substrate manufacturing methodaccording to this invention;

FIG. 3G is a diagram showing the substrate manufacturing methodaccording to this invention;

FIG. 4 is a diagram showing a relationship between temperature and timebefore and after CVD growth of graphene shown in a working example ofthis invention;

FIG. 5A is a perspective view showing a third working example of asemiconductor element according to this invention;

FIG. 5B is a perspective view showing the third working example of asemiconductor element according to this invention;

FIG. 6A is a perspective view showing a fourth working example of asemiconductor element according to this invention;

FIG. 6B is a perspective view showing the fourth working example of asemiconductor element according to this invention;

FIG. 6C is a perspective view showing the fourth working example of asemiconductor element according to this invention;

FIG. 7A is a cross-sectional view showing a fifth working example of asemiconductor element according to this invention;

FIG. 7B is a cross-sectional view showing the fifth working example of asemiconductor element according to this invention;

FIG. 7C is a cross-sectional view showing the fifth working example of asemiconductor element according to this invention;

FIG. 7D is a cross-sectional view showing the fifth working example of asemiconductor element according to this invention;

FIG. 7E is a cross-sectional view showing the fifth working example of asemiconductor element according to this invention;

FIG. 7F is a cross-sectional view showing the fifth working example of asemiconductor element according to this invention;

FIG. 8A is a cross-sectional view showing a sixth working example of asemiconductor element according to this invention;

FIG. 8B is a cross-sectional view showing the sixth working example of asemiconductor element according to this invention;

FIG. 8C is a cross-sectional view showing the sixth working example of asemiconductor element according to this invention;

FIG. 8D is a cross-sectional view showing the sixth working example of asemiconductor element according to this invention;

FIG. 8E is a cross-sectional view showing the sixth working example of asemiconductor element according to this invention;

FIG. 8F is a cross-sectional view showing the sixth working example of asemiconductor element according to this invention; and

FIG. 8G is a cross-sectional view showing the sixth working example of asemiconductor element according to this invention.

LIST OF REFERENCE NUMERALS

1 Substrate

2 Oxide layer

4 Graphene layer

4A Graphene substrate

5 Compound/alloyed layer

6 Atomic thin film

6B Atomic thin film substrate

9 Composite atomic layer thin film

9C Composite atomic layer thin film substrate

11 Substrate

12 Oxide layer

14 Graphene layer channel

14A Field-effect transistor (including graphene layer)

15 Silicide layer

16 Silicon atomic layer thin film channel

16B Field-effect transistor (including atomic layer thin film)

17 Source electrode

18 Drain electrode

19 Composite atomic layer thin film channel

19C Field-effect transistor (including composite atomic layer thin film)

21 Substrate

22 Oxide layer

23 Metal catalyst layer

24 Graphene layer

24A Graphene substrate

26 Atomic layer thin film

26B Atomic layer thin film substrate

29 Composite atomic layer thin film

29C Composite atomic layer thin film substrate

31 Silicon substrate

32 Silicon oxide layer

33 Nickel layer

34 Graphene layer

34A Graphene substrate

35 Silicide layer

41 Silicon substrate

42 Silicon oxide layer

43 Nickel catalyst layer

44 Graphene layer

44A Graphene substrate

45 Silicide layer

46 Silicon atomic layer thin film

46B Silicon atomic layer thin film substrate

51 Silicon substrate

52 Silicon oxide layer

53 Nickel catalyst layer

54 Graphene layer

54A Graphene substrate

55 Nickel silicide layer

57 Source electrode

58 Drain electrode

60 Field-effect transistor (including graphene layer)

61 Silicon substrate

62 Silicon oxide layer

63 Nickel catalyst layer

64 Graphene layer

64A Graphene substrate

65 Nickel silicide layer

66 Silicon atomic layer thin film

67 Source electrode

68 Drain electrode

70 Field-effect transistor (including silicon atomic layer thin film)

BEST MODE FOR CARRYING OUT THE INVENTION

Exemplary preferred embodiments of this invention will be described indetail, with reference to the accompanying drawings.

It should be understood that this invention is not limited to thefollowing embodiments and working examples, but may be modified invarious ways within the scope of the invention.

(Description of Configuration)

Referring to FIGS. 1A to 1C, an embodiment of this invention isillustrated. FIG. 1A is a perspective view of a graphene layer 4 and agraphene substrate 4A, FIG. 1B is a perspective view of an atomic layerthin film 6 and an atomic layer thin film substrate 6B, and FIG. 1C is aperspective view of a composite atomic layer thin film 9 and a compositeatomic layer thin film substrate 9C. As shown in FIG. 1A, the graphenelayer 4 is mounted on a layer (compound/alloyed layer 5) containing anoxide of a semiconductor or metal. The graphene layer 4 is formed by CVDusing a metal catalyst. The number of layers in the graphene layer 4 isone to about 30. The substrate 1 is formed of a semiconductor or ametal. The metal catalyst that has been used for growth of the graphenelayer 4 is absorbed as a compound/alloyed layer 5 at an interfacebetween an oxide layer 2 and the substrate 1 by diffusing through theoxide layer 2 into an upper layer of the substrate 1 to be combined oralloyed with the same. The substrate 1 not only functions to absorb themetal catalyst by combining or alloying the same but also functions tosupport the graphene layer 4 on the oxide layer 2. A structurecomprising the graphene layer 4, the oxide layer 2, the compound/alloyedlayer 5, and the substrate 1 is the graphene substrate 4A.

The graphene layer 4 and the graphene substrate 4A according to thisinvention bring about an advantageous effect that the graphene layer 4is insulated from the surroundings due to the fact that the graphenelayer 4 is located on the oxide layer 2. It can be assimilated to theeffect obtainable by SOI (Silicon On Insulator) substrates used in theexisting semiconductor industry. This effect is attributable to a uniquenew method of the present invention in which the metal catalyst, whichtends to short-circuit the graphene layer 4 in spite of being necessaryfor CVD growth of the graphene layer 4, is absorbed by the substrate 1through the oxide layer 2. Accordingly, the graphene layer 4 and thegraphene substrate 4A according to this invention can be directly usedfor the manufacture of semiconductor devices in the same manner asmonocrystal silicon substrates used in the existing semiconductorindustry. In particular, when a silicon substrate is used as thesubstrate 1, time-proven semiconductor technology can be applied to themanufacture of semiconductor devices comprising graphene, whicheliminates the need of any particular semiconductor manufacturingtechnology for graphene. As a result, an additional effect of reductionof development cost and manufacturing cost can be obtained. Anotherbenefit when a silicon substrate is used as the substrate 1 is obtainedfrom the presence of a silicide layer. In this case, the oxide layer 2is a silicon oxide layer, and the compound/alloyed layer 5 is a silicidelayer. Specifically, a benefit is obtained that the silicide layer canbe used as an electrode or wiring insulated from the graphene via thesilicon oxide layer. For example, the use of the substrate of thisinvention makes it possible to form a capacitor comprising the graphenelayer 4, a silicon oxide layer (oxide layer 2) and a silicide layer(compound/alloyed layer 5), or to form a gate stack comprising thegraphene layer 4 as a semiconductor channel, a silicon oxide layer(oxide layer 2) as a gate insulation layer, and a silicide layer(compound/alloyed layer 5) as a gate electrode. Further, while thegraphene layer 4 and the silicide layer (compound/alloyed layer 5) faceto each other in parallel, comprising the same shape and the same size,a lithography can be used to define the graphene layer 4 and a metalcatalyst layer which is to be the silicide layer (compound/alloyed layer5) in a desired shape, size and position, and then a suitable methodsuch as oxidation or the like can be used to remove the graphene layer4, whereby the silicide layer (compound/alloyed layer 5) is left as itis and can be used as wiring in the substrate.

An atomic layer thin film 6 and an atomic layer thin film substrate 6Bshown in FIG. 1B are obtained by oxidation-reduction of the graphenelayer 4 and the graphene substrate 4A shown in FIG. 1A. From a viewpointof compositional features, since the atomic layer thin film 6 is formedby an upper layer of the oxide layer 2 being partially reduced by thegraphene, the atomic layer thin film 6 is composed of semiconductor ormetallic elements comprising the oxide layer 2. From a viewpoint of thestructural features, the atomic layer thin film 6 is located on theoxide layer 2, that is, on an insulator suitable for production of theelement. Moreover, since the graphene, serving as a reducing agent, isultrathin in thickness, the atomic layer thin film produced byoxidation-reduction reaction also becomes ultrathin. Specifically, theatomic layer thin film 6 generally has a thickness of 10 nm or less, andthe minimum thickness is sub 1 nm. The compound/alloyed layer 5 locateddirectly under the oxide layer 2 is produced as a result of the metalcatalyst for growth of graphene being combined or being alloyed with theupper layer of the substrate 1. The atomic layer thin film substrate 6Bis the substrate composed of the atomic layer thin film 6, the oxidelayer 2, the compound/alloyed layer 5, and the substrate 1. The grapheneas the reducing agent functions as a sacrificial layer for forming theatomic layer thin film, and generally totally disappears as carbonmonoxide or carbon dioxide as a result of the oxidation reaction.However, as shown in FIG. 1C, only a lower part of the graphene layer 4can be intentionally used as a reducing agent while leaving an upperpart of the graphene layer 4, so that a composite atomic layer thin film9 comprising a two-layer structure including the graphene layer 4 andthe atomic layer thin film 6 derived from the oxide layer can beobtained. The composite atomic layer thin film substrate 9C is providedby this substrate composed of the graphene layer 4, the atomic layerthin film 6, the oxide layer 2, the compound/alloyed layer 5, and thesubstrate 1.

The atomic layer thin film 6 and the atomic layer thin film substrate 6Bhave the same effects as those of the graphene layer 4 and the graphenesubstrate 4A when the structural element of the atomic layer thin film 6is a semiconductor element. These effects are the same effects as thoseof the aforementioned SOI substrate. Especially when the substrate 1 isa silicon substrate, it serves as an ultimate SOI substrate. This isbecause a silicon layer on silicon oxide is an ultrathin silicon layerwith an ultimately small thickness. Accordingly, the atomic layer thinfilm 6 and the atomic layer thin film substrate 6B are expected to beutilized in a semiconductor device produced from an SOI substrate.Furthermore, when the structural element of the atomic layer thin film 6is a metallic element, the atomic layer thin film 6 can be used aswiring/electrode. Since this wiring/electrode is derived from a verythin graphene layer 4, an advantageous effect can be achieved that thefilm thickness is ultrathin.

The composite atomic layer thin film 9 and the composite atomic layerthin film substrate 9C provide two advantageous effects. The first oneis an effect that the thickness of the graphene layer 4 and the numberof layers of the graphene layer 4 are made controllable. The compositeatomic layer thin film 9 is formed, as described above, by using a partof the graphene layer 4 as a reducing agent to transform the oxide layer2 into a semiconductor or metallic atomic layer thin film 6.Accordingly, in a different viewpoint, the thickness of the graphenelayer 4 is decreased by the oxidation reaction with the oxide layer 2.The other effect is obtained when the composite atomic layer thin film 9is of a two-layer structure including the graphene layer 4 and a siliconatomic layer thin film (atomic layer thin film 6). When this compositeatomic layer thin film 9 is used as a channel of a semiconductorelement, the silicon atomic layer thin film (atomic layer thin film 6)serves as an impurity-doped layer as a carrier supply source, and thegraphene layer 4 serves as a carrier traveling layer. It can be liken toa channel of a HEMT (High Electron Mobility Transistor) in which asemiconductor region doped with a donor impurity supplying electrons andan active region where electrons travel are made of different compoundsemiconductors. In the case of an HEMT, since there is no impurity ionsin the electron traveling layer, electrons are not scattered by impurityions. Therefore, the mobility is increased by that much and more rapidoperation is possible. The composite atomic layer thin film 9 accordingto this invention also provides the same effect, and it can be expectedthat the high mobility that graphene inherently has is increased to itstheoretical limitation. Further, this invention is superior to the HEMTin that whereas the carrier is limited to electrons in the HEMT, eitherelectrons and electron holes can be used as the carrier to ensure highmobility according to this invention. This is because the silicon atomiclayer thin film (atomic layer thin film 6) can be doped with either adonor impurity or an acceptor impurity. No suitable doping method hasbeen known for graphene. Accordingly, from a different viewpoint, thisinvention is able to provide an effective pn conduction control methodwhile increasing the high mobility inherent to the graphene to itsutmost limit. This synergistic effect deserves special mention.

Referring to FIG. 2A, a perspective view including a cross-sectional(front) view of a semiconductor element comprising a graphene layeraccording to an embodiment of this invention is shown. A field-effecttransistor 14A is shown as an example of the semiconductor element.

In FIG. 2A, the reference numeral 11 indicates a silicon substrate, and12 indicates a silicon oxide layer. The silicon oxide layer 12 serves asa gate insulation layer for a gate electrode 15. The gate electrode 15has silicide produced by the metal catalyst layer for growth of graphenebeing absorbed by the interface between the silicon substrate 11 and thesilicon oxide layer 12. The gate electrode 15 functions to controlcarrier conduction in a graphene layer channel 14 located directly abovethe gate electrode 15. The graphene layer channel 14 is formed by CVDusing a metal catalyst, and functions to transport carriers between thesource electrode 17 and the drain electrode 18. Since the gate electrode15 is originally derived from the metal catalyst for growth of graphene,the gate electrode 15 has the same size and shape as those of thegraphene layer channel, and is located at the same two-dimensionalposition in a horizontal plane as the graphene layer channel. This meansthat this invention provides an advantageous effect that the gateelectrode 15 can be formed in a self-aligned manner with respect to thegraphene layer channel 14. The layer of the metal catalyst for growth ofgraphene can be formed to have an arbitrary size and shape at anarbitrary position by using a lithography technique, and hence thegraphene layer channel 14 and the gate electrode 15 can be defined to anarbitrary size, shape, and position. In this manner, a field-effecttransistor 14A comprising a graphene layer as a channel is produced.Since graphene possesses the highest mobility of all the materials, thefield-effect transistor 14A enjoys an ultrafast speed and ultralow powerconsumption. Further, since the field-effect transistor 14A is formed onthe silicon substrate, it exhibits high affinity with a semiconductortechnology using silicon as a base. This provides a benefit that thefield-effect transistor 14A can be mounted together with siliconsemiconductor elements, and a synergistic effect can be expected betweena graphene semiconductor element and a silicon semiconductor element. Itis also possible to produce a field-effect transistor comprising adouble-gate structure by forming a second gate electrode on the graphenelayer channel 14 between the source electrode 17 and the drain electrode18 through an insulator layer. When the double-gate structure isemployed, a benefit can be obtained that one of the gates is used fornormal control of channel conduction, and the other is used forthreshold control. Further, when the channel is formed of two graphenelayers, the double-gate structure makes it possible to increase the bandgap by applying an electric field to generate asymmetry between theupper and lower graphene layers. In this case, a benefit can be obtainedthat the on/off ratio is dramatically improved thanks to the band gapopening.

Referring to FIG. 2B, a perspective view including a (front)cross-sectional view is shown to illustrate a semiconductor elementcomprising an atomic layer thin film according to an embodiment of thisinvention.

Here, a field-effect transistor 16B is shown as an example of thesemiconductor element.

There are provided, as components, a silicon substrate 11, a siliconoxide layer 12, a gate electrode 15 comprising a silicide, a siliconatomic layer thin film channel 16, a source electrode 17, and a drainelectrode 18. As a whole, a field-effect transistor 16B comprising asilicon atomic layer thin film as a channel is provided. The functionsof the components are the same as described above. The silicon atomiclayer thin film channel 16 is formed by reducing a part of an upperlayer of the silicon oxide layer by a method using the graphene layer asa sacrificial layer. This provides an advantageous effect that thesilicide gate electrode 15 derived from a metal catalyst for formationof the graphene layer assumes a self-aligned position. Further, sincethe silicon atomic layer thin film channel 16 is characterized by beingso thin that it is difficult to form using a normal method, thefield-effect transistor 16B enjoys benefits of rapid operation and lowpower consumption. It is also possible to form a field-effect transistorcomprising a double-gate structure by forming a second gate electrode onthe silicon atomic layer thin film channel 16 between the sourceelectrode 17 and the drain electrode 18. The double-gate structureprovides an advantageous effect that one of the gates can be used fornormal control of channel conduction, and the other can be used forthreshold control.

Referring to FIG. 2C, a perspective view including a (front)cross-sectional view is shown to illustrate a semiconductor elementincluding a composite atomic layer thin film according to an embodimentof this invention.

Here, a field-effect transistor 19C is shown as an example of thesemiconductor element.

There are provided, as components, a silicon substrate 11, a siliconoxide layer 12, a gate electrode 15 comprising a silicide, a compositeatomic layer thin film channel 19 including a graphene layer channel 14as an upper layer and a silicon atomic layer thin film channel 16 as alower layer, a source electrode 17, and a drain electrode 18. As awhole, a field-effect transistor 19C comprising a composite atomic layerthin film as a channel is formed. The functions of the components arethe same as described above. The composite atomic layer thin filmchannel 19 is formed by reducing a part of an upper layer of the siliconoxide layer by a method using a part of the graphene layer as asacrificial layer. The silicon atomic layer thin film channel 16 servesas a charge supply layer, and the graphene layer channel 14 serves as acarrier transfer layer, whereby a benefit is obtained that thefield-effect transistor 19C is enabled operate at a ultrahigh speedrealized by maximizing the high mobility that graphene inherently has.Obviously, a benefit can also be obtained that the power consumption isreduced to its ultimate limit. It is also possible to form afield-effect transistor comprising a double-gate structure by forming asecond gate electrode on the graphene layer channel 14 between thesource electrode 17 and the drain electrode 18 through an insulatorlayer. When the double-gate structure is employed, an advantageouseffect can be obtained that one of the gates is used for normal controlof channel conduction and the other is used for threshold control.

(Description of Manufacturing Method)

Referring to FIGS. 3A to 3G, a manufacturing method according to anembodiment of the invention will be described. FIGS. 3A to 3E illustratea fabrication method of a graphene layer 24 and a graphene substrate24A, and FIGS. 3A to 3F illustrate a fabrication method of an atomiclayer thin film 26 and an atomic layer thin film substrate 26A, andFIGS. 3A to 3E and FIG. 3G illustrate a fabrication method of acomposite atomic layer thin film 29 and a composite atomic layer thinfilm substrate 29C.

FIGS. 3A to 3E illustrate a fabrication method of the graphene layer 24and the graphene substrate 24A. First, an appropriate substrate 21 isprepared as shown in FIG. 3A. The substrate material is a semiconductoror a metal, and is at least one selected from the group consisting ofboron (B), aluminum (Al), silicon (Si), scandium (Sc), titanium (Ti),vanadium (V), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co),nickel (Ni), copper (Cu), zinc (Zn), germanium (Ge), zirconium (Zr),niobium (Nb), molybdenum (Mo), ruthenium (Ru), palladium (Pd), silver(Ag), hafnium (Hf), tantalum (Ta), tungsten (W), rhenium (Re), osmium(Os), iridium (Ir), bismuth (Bi), gallium arsenide (GaAs), indiumphophide (InP), indium antimonide (InSb), GaN (gallium nitride), AlN(aluminum nitride), and silicon carbide (SiC). Subsequently, as shown inFIG. 3B, a layer containing an oxide of a semiconductor or metal (oxidelayer 22) is formed on the substrate 21. The formation of the oxidelayer 22 may be performed not only by a film formation method such assputtering, deposition and coating, but also by a method of thermallyoxidizing the substrate itself. The material for the oxide layer may beany one or a combination selected from the group consisting of lithiumoxide (I)/Li₂O, beryllium oxide (II)/BeO, boron oxide (II)/B₂O₃, sodiumoxide (I)/Na₂O, magnesium oxide (II)/MgO, aluminum oxide (III)/Al₂O₃,silicon oxide (IV)/SiO₂, phosphorus oxide (V)/P₄O₁₀, phosphorus oxide(IV)/PO₂, potassium oxide (I)/K₂O, calcium oxide (II)/CaO, scandiumoxide (III)/Sc₂O₃, titanium oxide (IV)TiO₂, titanium oxide (III,IV)Ti₃O₅, titanium oxide (III)/Ti₂O₃, titanium oxide (II)/TiO, vanadiumoxide (V)N₂O₅, vanadium oxide (IV)/VO₂, vanadium oxide (III)/V₂O₃,vanadium oxide (II)NO, chromium oxide (II)/CrO, chromium oxide(II,III)Cr₃O₄, chromium oxide (III)/Cr₂O₃, manganese oxide (IV)/MnO₂,manganese oxide (III)/Mn₂O₃, manganese oxide (II,III)/Mn₃O₄, manganeseoxide (II)/MnO, iron oxide (III)/Fe₂O₃, iron oxide (II)/FeO, ironoxide(II,III)/Fe₃O₄, cobalt oxide (II,III)/Co₃O₄, cobalt oxide (II)CoO,nickel oxide (II)/NiO, copper oxide(II)/CuO, copper oxide(I)/Cu₂O, zincoxide (II)/ZnO, gallium oxide(III)/Ga₂O₃, germanium oxide (IV)/GeO₂,arsenic oxide (III)/As₂O₃, selenium oxide (IV)/SeO₂, rubidium oxide(IV)/RuO₂, strontium oxide (II)/SrO, yttrium oxide (III)/Y₂O₃, zirconiumoxide (IV)/ZrO₂, niobium oxide (V)/Nb₂O₅, niobium oxide (IV)/NbO₂,niobium oxide (II)/NbO, molybdenum oxide (VI)/MoO₃, molybdenum oxide(IV)/MoO₂, ruthenium oxide (VI)/RuO₃, ruthenium oxide (VIII)/RuO₄,ruthenium oxide (IV)/RuO₂, rhodium oxide(III)/Rh₂O₃, palladium oxide(II)/PdO, silver oxide (I)/Ag₂O, cadmium oxide (II)/CdO, indium oxide(III)/In₂O₃, tin oxide (IV)/SnO₂, antimony oxide(III)/Sb₂O₃, telluriumoxide (IV)/TeO₂, barium oxide (II)/BaO, cerium oxide (IV)/CeO₂, ceriumoxide (III)/Ce₂O₃, praseodymium oxide (III)/Pr₂O₃, neodymium oxide(III)/Nd₂O₃, samarium oxide (III)/Sm₂O₃, europium oxide (III)/Eu₂O₃,gadolinium oxide (III)/Gd₂O₃, terbium oxide (III)/Tb₂O₃, dysprosiumoxide (III)/Dy₂O₃, hafnium oxide (IV)/HfO₂, tantalum oxide (V)/Ta₂O₅,tungsten oxide (VI)/WO₃, tungsten oxide (IV)/WO₂, rhenium oxide(IV)/ReO₂, osmium oxide (IV)/OsO₂, iridium oxide (IV)/IrO₂, mercuryoxide (I)/Hg₂O, lead oxide (IV)/PbO₂, lead oxide (II,III)/Pb₃O₄, leadoxide (II)/PbO, bismuth oxide (III)/Bi₂O₃, thorium oxide (IV)/ThO₂, anduranium oxide (IV)/UO₂. Subsequently, as shown in FIG. 3C, a layercomprising a metal catalyst required for growth of graphene (metalcatalyst layer 23) is formed. The formation of the metal catalyst layer23 may be performed by a film formation method such as sputtering ordeposition. The metal catalyst contains at least a metal element, anddesirably contains any one of chromium (Cr), manganese (Mn), iron (Fe),cobalt (Co), nickel (Ni), copper (Cu), molybdenum (Mo), ruthenium (Ru),rhodium (Rh), palladium (Pd), silver (Ag), tungsten (W), rhenium (Re),osmium (Os), iridium (Ir), platinum (Pt), and gold (Au). After that, asshown in FIG. 3D, CVD growth is performed on the metal catalyst layer 23using a carbon source as a material to form the graphene layer 24. TheCVD growth is performed within a temperature range of 500 to 1200° C.The temperature range should be set, according types of the metalcatalyst and the oxide, such that the catalyst metal is not dissipatedin the oxide layer 22. The carbon source usable for this purpose is asaturated hydrocarbon such as methane gas, ethane, propane, and butane,an unsaturated hydrocarbon such as ethylene, acetylene, and benzene, oran alcohol such as methyl alcohol and ethyl alcohol, or carbon monoxide.After the growth of graphene, as shown in FIG. 3E, the metal catalystlayer 23 is diffused into the oxide layer 22 to be combined or alloyedwith a material forming the substrate 21 at the interface between theoxide layer 22 and the substrate 21, so that a compound or alloyed layer25 is formed. The diffusion, combination and alloying of the metalcatalyst layer 23 are performed by heating. The temperature for heating,that is the temperature for diffusion, combination and alloying is setin a range of 500 to 1500° C. However, the temperature should be set insuch a range that no oxidation-reduction reaction occurs between thegraphene layer 24 and the oxide layer 22. In this manner, the graphenelayer 24 and the graphene substrate 24A are completed.

FIGS. 3A to 3F illustrate a fabrication method of the atomic layer thinfilm 26 and an atomic layer thin film substrate 26B. The fabricationmethod shown in FIGS. 3A to 3E is the same as the fabrication method ofthe graphene layer 24 and the graphene substrate 24A. As shown in FIG.3F, a part of an upper layer of the oxide layer is reduced by heating tocause the entire graphene layer 24 to serve as a reducing agent, wherebythe atomic layer thin film 26 is formed. As a result, the atomic layerthin film substrate 26B is obtained, comprising the atomic layer thinfilm 26, the oxide layer 22, and the compound or alloyed layer 25, andthe substrate 21. During this process, the graphene layer 24 serving asa sacrificial layer is oxidized and completely disappears in the gasphase as carbon monoxide or carbon dioxide, while only the atomic layerthin film 26 is left, comprising a semiconductor or metallic elementwhich forms the oxide layer 22 by carbon reduction. The heatingtemperature during this process is set to be equal to or higher than atemperature level at which oxidation-reduction reaction occurs.Specifically, the heating temperature is set to a range from 500 to3500° C. In case the substrate or the like is not resistant enough tohigh temperature, only the area requiring oxidation-reduction may beheated locally and briefly by using laser annealing or the like.

FIGS. 3A to 3E and FIG. 3G illustrate a fabrication method of thecomposite atomic layer thin film 29 and the composite atomic layer thinfilm substrate 29C. The fabrication method shown in FIGS. 3A to 3E is incommon with those of the graphene layer 24 and the graphene substrate24A. As shown in FIG. 3G, a part of an upper layer of the oxide layer 22is reduced by heating to use a part of a lower layer of the graphenelayer 24 as a reducing agent, whereby the composite atomic layer thinfilm substrate 29C is obtained, comprising the composite atomic layerthin film 29 including the graphene layer 24 as the upper layer and theatomic layer thin film 26 as the lower layer, the composite atomic layerthin film 29, the oxide layer 22, the compound or alloyed layer 25, andthe substrate 21. During this process, the lower layer of the graphenelayer 24 serving as a sacrificial layer is oxidized and completelydisappears in the gas phase as carbon monoxide or carbon dioxide, whilethe upper layer of the graphene layer 24 is left. The atomic layer thinfilm 26 comprising a semiconductor or metallic element which forms theoxide layer 22 by carbon reduction is left, comprising the interface incommon with the graphene layer 24. The heating temperature during thisprocess is set to be equal to or higher than a temperature level atwhich oxidation-reduction reaction occurs. In order to precisely controlthe heating temperature and heating time, laser annealing is suitable.

Working Example 1 CVD Growth of Graphene Layer and Dependency on MetalCatalyst

The graphene layer 24 and the graphene substrate 24A were fabricatedaccording to the fabrication method shown in FIGS. 3A to 3E. A siliconsubstrate as the substrate 21 was thermally oxidized to form a siliconoxide layer (oxide layer 22), and then iron, nickel and copper as metalcatalysts were sputtered to form a film, respectively. Using each ofthese metal catalysts, CVD growth of graphene was performed at atemperature of 1000° C., using methane as a carbon source. FIG. 4represents a typical thermal profile before and after the CVD growth ofgraphene. The CVD growth was performed in the procedures as describedbelow. The substrate comprising the metal catalyst film formed thereonwas heated from room temperature to a CVD growth temperature under theflow of gas mixture of hydrogen and argon, and the CVD growthtemperature was kept for about 10 to 60 minutes to age the metalcatalysts. After that, flow of gas mixture of hydrogen and methane wassupplied for from 30 seconds to 30 minutes to let the graphene layer 24grow. Finally, the substrate was cooled to room temperature under theflow of gas mixture of hydrogen and argon. A surface of the growngraphene was observed with an atomic force microscope or a scanningelectron microscope. The result revealed that a satisfactory graphenelayer 24 could be formed no matter which of iron, nickel and copper wasused as the metal catalyst. The number of layers of the graphene layer24, which could be controlled depending on the type of catalyst, the CVDgrowth temperature, and the CVD growth, was one to about 30 layers.

Working Example 2 CVD Growth of Graphene Layer and Dependency on CVDGrowth Conditions

Effects of CVD growth conditions on growth of graphene when the metalcatalyst was nickel were examined. Examined growth parameters weretemperature drop rate [° C./min] after CVD growth, and methaneconcentration [% by volume] in gas mixture of argon, hydrogen andmethane. The other CVD growth conditions including metal catalyst agingconditions and graphene growth temperature (1000° C.) were keptconstant. Surface of grown graphene was evaluated with the use of anatomic force microscope, a scanning electron microscope or the like.Table 1 shows a relationship between temperature drop rate and methaneconcentration given to the growth of graphene, and summarizes featuresof graphene obtained under each condition. What is noticeable in thefirst place is that when the methane concentration was 0.25% by volume,little growth of graphene was observed no matter how much is thetemperature drop rate, whereas when the methane concentration was 1.00%by volume or more, multilayer graphene (including of more than twolayers) constituted a large part regardless of temperature drop rate.Growth of one- or two-layer graphene was observed when the methaneconcentration was 0.50 to 0.75% by volume, and the temperature drop ratewas 25° C./min. Having an overview of the result, the multilayergraphene is obtained more likely when the methane concentration is high,whereas one- or two-layer graphene is obtained more likely when thetemperature drop rate is low. More particularly, in order to obtainmultilayer graphene, the methane concentration must be set to 1.00% byvolume or more, or the methane concentration must be set to 0.50 to0.75% by volume while the temperature drop rate is set to 50° C./min orhigher. In order to obtain one- or two-layer graphene, the methane gasconcentration must be set to 0.50 to 0.75% by volume while thetemperature drop rate is kept at 25° C./min or lower.

TABLE 1 Temperature drop rate Methane concentration in gas mixture [% byvolume] [° C./min] 0.25 0.5 0.75 1 100 No graphene No grapheneMultilayer Multilayer 50 growth growth graphene graphene 25 One- or One-or 5 two-layer two-layer graphene graphene

Working Example 3 Fabrication of Graphene Layer and Graphene Substrate

A graphene layer was formed on a comb-like electrode structure 33 asshown in FIG. 5A in the same manner as in the fabrication method shownin FIGS. 3A to 3E to fabricate a graphene substrate.

FIG. 5A shows a comb-like electrode structure in which a nickel catalystlayer 33 has been vapor deposited on a silicon oxide layer 32/siliconsubstrate 31 by being defined by lithography. CVD growth of graphene wasperformed on this comb-like nickel catalyst layer 33 under theconditions indicated in working example 2. Observation with scanningelectron microscope or the like revealed that graphene layers 34including one- or two-layer graphene and of multilayer graphene wereformed on the comb-like electrode structure (nickel catalyst layer 33)depending on the CVD conditions such as methane concentration andtemperature drop rate. Consequently, the graphene layer 34/nickelcatalyst layer 33/silicon oxide layer 32/silicon substrate 31 was heatedat 1200° C. for 6 hours under vacuum or inert atmosphere, resulting in astructure shown in FIG. 5B. The observation with a scanning electronmicroscope revealed that the graphene layer 34 was located not on thenickel catalyst layer 33 but on the silicon oxide layer 32. Further, asa result of analysis by SIMS (Secondary Ionization Mass Spectrometry),it was confirmed that a silicide layer 35 was located at the interfacebetween the silicon oxide layer 32 and the silicon substrate 31. Thismeans that the nickel catalyst layer was diffused into the silicon oxidelayer and reacted with silicon at the interface. Accordingly, thelayered structure of the substrate includes the graphene layer 34, thesilicon oxide layer 32, the silicide layer 35, and the silicon substrate31, and it was proved that a graphene substrate 34A comprising the samestructure as that of the graphene layer 4 and the graphene substrate 4Ashown in FIG. 1A was fabricated.

Working Example 4 Fabrication of Atomic Thin Film and Atomic Thin FilmSubstrate

An atomic layer thin film was formed on a comb-like electrode structureas shown in FIG. 5A to fabricate an atomic layer thin film substrate inthe same manner as the fabrication method shown in FIGS. 3A to 3F.

FIG. 6A shows a comb-like electrode structure which has been produced bya method in which a silicon oxide layer 42 is formed on a siliconsubstrate 41 by thermal oxidation and then a nickel catalyst layer 43 isformed thereon by being defined by lithography. FIG. 6B shows a resultobtained after growth of graphene and interface silicidation wereperformed in the same manner as in the working example 3. This structurewas analyzed in the same manner as in the working example 3, whereby itwas revealed that the structure was a graphene substrate 44A comprisinga stacked structure including a graphene layer 44, the silicon oxidelayer 42, a silicide layer 45, and the silicon substrate 41.Subsequently, this graphene substrate 44A was heated at 1700° C. for 6hours under vacuum or inert atmosphere. FIG. 6C shows a result thusobtained. It should be noted that this heating temperature exceeds atemperature of 1668° C. at which silicon oxide is reduced by carbon. Asa result of surface observation with an atomic force microscope orscanning electron microscope and analysis by EDX (Energy DispersiveX-ray Spectrometry), it was confirmed that the comb-like electrode onthe surface of the structure shown in FIG. 6C was an ultrathin siliconatomic layer thin film. The thickness of the silicon atomic layer thinfilm 46 was dependent on the thickness of the graphene layer, and theminimum was sub 1 nm and the maximum was about 10 nm. Therefore, thestacked structure of the substrate thus fabricated was composed of thesilicon atomic layer thin film 46, the silicon oxide layer 42, thesilicide layer 45, and the silicon substrate 41, and hence it was provedthat an atomic layer thin film and an atomic layer thin film substratewere fabricated. It was also confirmed that when the graphene substratewas heated by using laser heating in place of the aforementioned heatingmethod while strictly controlling the heating time, only an upper partof the graphene layer could be left and a silicon atomic layer thin filmcould be formed directly under the left part of the graphene layer. Thestacked structure of the substrate produced in this manner was composedof a graphene layer, a silicon atomic layer thin film, a silicon oxidelayer, a silicide layer, and a silicon substrate, and it was proved thata composite atomic layer thin film and a composite atomic layer thinfilm substrate were fabricated.

Working Example 5 Fabrication of Field-Effect Transistor Having GrapheneLayer as Channel

A field-effect transistor comprising a graphene layer as a channel wasfabricated by a method according to this invention. A silicon substrate51 was prepared as shown in FIG. 7A. As shown in FIG. 7B, a siliconoxide layer 52 was formed on the silicon substrate 51 by CVD with silanegas and oxygen. As shown in FIG. 7C, a nickel catalyst layer 53 forgrowth of graphene was laid out on the silicon oxide layer 52 by beingdefined with lithography. The substrate of FIG. 7C was introduced into aCVD apparatus, in which CVD growth of a graphene layer 54 (of one or twolayers) was performed on the nickel catalyst layer 53 in gas mixture ofargon, hydrogen and methane (methane concentration of 0.5% by volume),at a temperature of 1000° C., for duration of 5 minutes, and at atemperature drop rate of 0.5° C./min as shown in FIG. 7D. The graphenelayer 54 eventually serves as a channel. Subsequently, as shown in FIG.7E, the substrate of FIG. 7D was vacuum-heated at 1200° C. for 6 hours,whereby the nickel catalyst layer 53 was diffused into the silicon oxidelayer 52 to be reacted with silicon in an upper layer of the siliconsubstrate so that it was absorbed as a nickel silicide layer 55 at theinterface between the silicon oxide layer 52 and the silicon substrate51. The nickel silicide layer 55 was formed in a self-aligned manner andfunctions as a gate electrode. Finally, a graphene substrate 54A asshown in FIG. 7F was defined by lithography so that gold was vapordeposited on each of the graphene layer 54 to form a source electrode 57and a drain electrode 58. In this manner, a field-effect transistor 60including a graphene layer was obtained. The gate electrode, the sourceelectrode, and the drain electrode of this field-effect transistor 60were interconnected and electrical measurement was conducted. As aresult, favorable transistor operation was confirmed.

Working Example 6 Fabrication of Field-Effect Transistor Having SiliconAtomic Thin Film as Channel

A field-effect transistor comprising a silicon atomic layer thin film asa channel was fabricated by a method according to this invention.Firstly, a silicon substrate 61 as shown in FIG. 8A was prepared. Then,a silicon oxide layer 62 was formed on the silicon substrate 61 by CVDwith mixture gas of silane gas and oxygen as shown in FIG. 8B. A nickelcatalyst layer 63 for growth of graphene was laid out on the siliconoxide layer by being defined with lithography as shown in FIG. 8C.Subsequently, the substrate of FIG. 8C was introduced into a CVDapparatus, in which CVD growth of a graphene layer 64 (of one or twolayers) was performed in gas mixture of argon, hydrogen and methane(methane concentration of 0.5% by volume), at a temperature of 1000° C.,for duration of 5 minutes, and at a temperature drop rate of 0.5° C./minas shown in FIG. 8D. As described later, the graphene layer 64 is asacrificial layer serving as a reducing agent for silicon oxide. Afterthe growth of the graphene layer 64, as shown in FIG. 8E, the substrateof FIG. 8D was vacuum-heated at 1200° C. for 6 hours, whereby the nickelcatalyst layer 63 was diffused into the silicon oxide layer 62 to reactwith silicon in an upper layer of the silicon substrate, whereby it wasabsorbed as a nickel silicide layer 65 at the interface between thesilicon oxide layer 62 and the silicon substrate 61. The nickel silicidelayer 65 was formed in a self-aligned manner and functions as a gateelectrode. Subsequently, as shown in FIG. 8F, a graphene substrate 64Awas vacuum-heated at 1700° C. for 6 hours, so that a silicon atomiclayer thin film 66 was formed by oxidation-reduction reaction betweenthe graphene layer 64 and an upper layer of the silicon oxide layer 62.The silicon atomic layer thin film 66 serves as a channel. Finally, asilicon atomic layer thin film substrate 66B as shown in FIG. 8G wasdefined by lithography so that gold was vapor deposited on each of thesilicon atomic layer thin film 66 to form a source electrode 67 and adrain electrode 68. In this manner, a field-effect transistor 70including a silicon atomic layer thin film was obtained. The gateelectrode, the source electrode, and the drain electrode on thefield-effect transistor 70 were interconnected by a known method, andelectrical measurement was conducted. As a result, favorable transistor,operation was confirmed. Further, it was confirmed in the manufacturingmethod shown in FIGS. 8A to 8G that when the CVD growth conditionsduring the growth of graphene of FIG. 8D were changed so as to produce amultilayer graphene, and the heating method used in oxidation-reductionof FIG. 8F was changed to laser heating so as to shorten the duration ofoxidation-reduction, a composite atomic layer thin film comprising agraphene layer and a silicon atomic layer thin film could be obtained.As a result, a field-effect transistor including a composite atomiclayer thin film also could be produced, and it was confirmed that thisfield-effect transistor had favorable transistor performance.

As described above, this invention provides advantageous effects asdescribed below.

(First Effect)

It is possible to provide a high-quality and large-area graphenesubstrate in which there is no structural defect or wrinkles ingraphene, and there is no deposition of impurities which may inhibitcarrier transportation, and also to provide a manufacturing method ofsuch a graphene substrate.

(Second Effect)

It is made possible, by causing graphene to exhibit its inherent,excellent electronic properties sufficiently, to provide a semiconductordevice which is made from the aforementioned graphene substrate, capableof increasing operation speed, reducing power consumption, andincreasing degree of integration, and thus has improved reliability andproductivity. It is also possible to provide a manufacturing method ofsuch a semiconductor device.

(Third Effect)

It is possible to provide a high-quality, ultrathin and large-areaatomic layer thin film substrate with high versatility and lowproduction cost, which is composed of a wide variety of semiconductor ormetallic elements, and also possible to provide a manufacturing methodof such an atomic layer thin film substrate.

(Fourth Effect)

It is possible to provide a semiconductor device which is made from theaforementioned atomic layer thin film, and is capable of increasingoperation speed, reducing power consumption, and increasing degree ofintegration, and thus has improved reliability and productivity. It isalso made possible to provide a manufacturing method of such asemiconductor device.

INDUSTRIAL APPLICABILITY

This invention is applicable, for example, to semiconductor devices inelectronics field characterized by low power consumption and ultrahighoperation speed such as field-effect transistors, logic circuits, memoryelement circuits, and AD converts, as well as semiconductor devices inoptoelectronics field operable in terahertz electromagnetic wavebandsuch as amplifiers transmitters, light sources, lasers, andultrahigh-speed broadband information communication equipment.

This application is based upon and claims the benefit of priority fromJapanese Patent Application No. 2009-190948, filed Aug. 20, 2009, thedisclosure of which is incorporated herein in its entirety by reference.

1. A substrate formed by stacking, on a semiconductor or metal layer, agraphene layer formed by chemical vapor deposition using a metalcatalyst, an oxide layer for diffusing the metal catalyst, and acompound or alloyed layer formed by combination or alloying between themetal catalyst and the semiconductor or metal layer, wherein thesubstrate, the compound or alloyed layer, the oxide layer, and thegraphene layer is stacked in this order.
 2. A substrate formed bystacking, on a semiconductor or metal layer, an atomic layer thin filmformed by reducing an oxide layer with a graphene layer formed bychemical vapor deposition using a metal catalyst, the oxide layer fordiffusing the metal catalyst, and a compound or alloyed layer formed bycombination or alloying between the metal catalyst and the semiconductoror metal layer, wherein the substrate, the compound or alloyed layer,the oxide layer, and the atomic layer thin film is stacked in thisorder.
 3. A substrate formed by stacking, on a semiconductor or metallayer, a graphene layer formed by chemical vapor deposition using ametal catalyst, an atomic layer thin film formed by reducing an oxidelayer with the graphene layer, the oxide layer for diffusing the metalcatalyst, and a compound or alloyed layer formed by combination oralloying between the metal catalyst and the semiconductor or metallayer, wherein the substrate, the compound or alloyed layer, the oxidelayer, the atomic layer thin film, and the graphene layer is stacked inthis order.
 4. The substrate as claimed in claim 1, wherein the metalcatalyst is at least one selected from the group consisting of chromium(Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu),molybdenum (Mo), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver(Ag), tungsten (W), rhenium (Re), osmium (Os), iridium (Ir), platinum(Pt), and gold (Au).
 5. The substrate as claimed in claim 1, claim 1,wherein the oxide layer is formed of at least one selected from thegroup consisting of lithium oxide (I)/Li₂O, beryllium oxide (II)/BeO,boron oxide (II)/B₂O₃, sodium oxide (I)/Na₂O, magnesium oxide (II)/MgO,aluminum oxide (III)/Al₂O₃, silicon oxide (IV)/SiO₂, phosphorus oxide(V)/P₄O₁₀, phosphorus oxide (IV)/PO₂, potassium oxide (I)/K₂O, calciumoxide (II)/CaO, scandium oxide (III)/Sc₂O₃, titanium oxide (IV)TiO₂,titanium oxide (III, IV)/Ti₃O₅, titanium oxide (III)/Ti₂O₃, titaniumoxide (II)/TiO, vanadium oxide (V)N₂O₅, vanadium oxide (IV)/VO₂,vanadium oxide (III)/V₂O₃, vanadium oxide (II)/VO, chromium oxide(II)/CrO, chromium oxide (II,III)/Cr₃O₄, chromium oxide (III)/Cr₂O₃,manganese oxide (IV)/MnO₂, manganese oxide (III)/Mn₂O₃, manganese oxide(II,III)/Mn₃O₄, manganese oxide (II)/MnO, iron oxide (III)/Fe₂O₃, ironoxide (II)/FeO, iron oxide (II,III)/Fe₃O₄, cobalt oxide (II,III)/Co₃O₄,cobalt oxide (II)/CoO, nickel oxide (II)/NiO, copper oxide (II)/CuO,copper oxide (I)/Cu₂O, zinc oxide (II)/ZnO, gallium oxide (III)/Ga₂O₃,germanium oxide (IV)/GeO₂, arsenic oxide(III)/As₂O₃, selenium oxide(IV)/SeO₂, rubidium oxide (IV)/RuO₂, strontium oxide (II)/SrO, yttriumoxide (III)/Y₂O₃, zirconium oxide (IV)/ZrO₂, niobium oxide (V)/Nb₂O₅,niobium oxide (IV)/NbO₂, niobium oxide (II)/NbO, molybdenum oxide(VI)/MoO₃, molybdenum oxide (IV)/MoO₂, ruthenium oxide (VI)/RuO₃,ruthenium oxide (VIII)/RuO₄, ruthenium oxide (IV)/RuO₂, rhodium oxide(III)/Rh₂O₃, palladium oxide (II)/PdO, silver oxide (I)/Ag₂O, cadmiumoxide (II)/CdO, indium oxide (III)/In₂O₃, tin oxide (IV)/SnO₂, antimonyoxide (III)/Sb₂O₃, tellurium oxide (IV)/TeO₂, barium oxide (II)/BaO,cerium oxide (IV)/CeO₂, cerium oxide (III)/Ce₂O₃, praseodymium oxide(III)/Pr₂O₃, neodymium oxide (III)/Nd₂O₃, samarium oxide (III)/Sm₂O₃,europium oxide (III)/Eu₂O₃, gadolinium oxide (III)/Gd₂O₃, terbium oxide(III)/Tb₂O₃, dysprosium oxide (III)/Dy₂O₃, hafnium oxide (IV)/HfO₂,tantalum oxide (V)/Ta₂O₅, tungsten oxide (VI)/WO₃, tungsten oxide(IV)/WO₂, rhenium oxide (IV)/ReO₂, osmium oxide (IV)/OsO₂, iridium oxide(IV)/IrO₂, mercury oxide (I)/Hg₂O, lead oxide (IV)/PbO₂, lead oxide(II,III)/Pb₃O₄, lead oxide (II)/PbO, bismuth oxide (III)/Bi₂O₃, thoriumoxide(IV)/ThO₂, and uranium oxide (IV)/UO₂.
 6. The substrate as claimedin claim 1, wherein the semiconductor or metal layer is formed of atleast one selected from the group consisting of boron (B), aluminum(Al), silicon (Si), scandium (Sc), titanium (Ti), vanadium (V), chromium(Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu),zinc (Zn), germanium (Ge), zirconium (Zr), niobium (Nb), molybdenum(Mo), ruthenium (Ru), palladium (Pd), silver (Ag), hafnium (Hf),tantalum (Ta), tungsten (W), rhenium (Re), osmium (Os), iridium (Ir),bismuth (Bi), gallium arsenide (GaAs), indium phophide (InP), indiumantimonide (InSb), GaN (gallium nitride), AlN (aluminum nitride), andsilicon carbide (SiC).
 7. A semiconductor element manufactured with thesubstrate as claimed in claim
 1. 8.-19. (canceled)